Job Description
· Own verification of entire FPGA design used in high-end router products
· Understand design specifications and interact with design engineers to identify verification scenarios
· Create test plans, constrained-random verification environments, testcases, regressions, and coverage reports
Identify and write all types of coverage measures for stimulus and corner-cases
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Required Skills & Experience
· Strong academic background in Electrical Engineering (Bachelor’s required, Master’s preferred)
· 7–10 years of pure verification experience in ASIC/FPGAs
· Proficient in SystemVerilog with clear OOP concepts
· Experience developing object-oriented testbench infrastructure, BFMs, and testcases in UVM
· Experience with PCIe, Ethernet, slow speed interfaces like I2C, SPI, MDIO, etc.
· Understanding of verifying IP integrations, strategies, corner cases, etc.
· Ability to independently develop test plans, test sequences, generate stimuli, and collaborate with RTL designers to debug failures
· Experience with scripting languages like Perl, Python is a plus
Proficiency with industry-standard tools, revision control systems, and regression systems
Benefit packages for this role will start on the 1st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.