Staff PMIC Design Engineer

We are seeking a Staff Engineer, Analogue PMIC Design to serve as a senior individual contributor within an ASIC engineering organization. This role is responsible for end-to-end ownership of analog power management blocks, including architecture definition, circuit design, simulation, verification, and documentation. The Staff Engineer partners closely with system architects, digital design, and verification teams to deliver fully validated PMIC IP used in large scale consumer SoCs. This position focuses on designing power blocks such as SMPS and LDOs, solving complex analog problems under tight power and area constraints, and ensuring designs meet performance across all process and voltage corners.

ADDITIONAL RESPONSIBILITIES:
- Definition of the architecture for the complex Power-management blocks, plan and execute the development of the blocks and providing the necessary documentation to different departments for the characterization of the block.
- Responsible for the delivering the fully verified blocks and may get involved in the verification of power-management subsystems within the Analogue section of a chip
- Solves complex problems in a tightly constrained environment;
- Fully competent in Analogue design for complex sub-cells and small subsystems;
- Keeps abreast of new developments and is technical expert in the design of analogue sub-cells;
- Ensures quality of the solution; works with macro lead to ensure timely delivery of subsystems

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to HR@insightglobal.com.To learn more about how we collect, keep, and process your private information, please review Insight Global's Workforce Privacy Policy: https://insightglobal.com/workforce-privacy-policy/.

- Bachelor's degree, master's degree, or PHD in Science, Engineering, or related field
- 10+ years of experience in analog or mixed signal IC design
- Experience of using Cadence and Mentor analogue design and verification tools
- hands on ownership of PMIC or power related IP blocks
- Experience delivering fully verified blocks to tape out
- Experience on low power consumer or mobile SoCs

- Experience supporting bring up or validation teams
- Design experience of Key Power management IPs like SMPS, LDOs
- Experience with additional power blocks such as bandgaps, references, charge pumps, or clock generators
- Exposure to automotive or high reliability power designs
- Familiarity with low power system level architecture tradeoffs
- Familiarity with CMOS process technologies

Benefit packages for this role will start on the 1st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.