-Circuit architecture, planning, design, simulation, verification, and production ramp support of highly integrated, high-volume ICs for high-growth, fast-paced, and competitive wireless handset market
- Knowledge of RF area circuit experience a plus
-Familiarity with cellular standards will be useful
- Good understanding of semiconductor physics and strong circuit intuition/simulation skills utilizing Cadence is necessary
-115,000-150,000
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- BSEE and 8 years experience required, or MSEE and 6 years, or PhD and 3 years. MSEE preferred
- Demonstrated Analog IC design experience using SOI CMOS
- Proficient with Cadence tools and solid understanding of general analog circuits such as bias, bandgap, LDO, opamp, charge pump, temperature sensor and etc
- Experienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on IC
- Strong understanding of silicon fabrication and how it affects the device physics, device model, and circuit performance
- Demonstrated experience debugging, resolving and applying techniques to mitigate analog signal noise coupling and optimum layout for performance, and die size trade off
- Layout experience using Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on analog layouts
- Good understanding of MIPI standard
- Good communication and presentation skills
Benefit packages for this role will start on the 31st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.