Silicon DD Engineer V

Post Date

Feb 09, 2023

Location

Redmond,
Washington

ZIP/Postal Code

98052
US
Jul 19, 2024 Insight Global

Job Type

Contract

Category

Engineer

Req #

VMS-MET-41586-1

Pay Rate

$103 - $125 (hourly estimate)

Job Description

Digital Design Engineer CW - JD
Target Level: Senior

This role can be remote but must be in PST timezone.
Key Responsibilities:
Implement design/testbench in SystemVerilog
Integrate IP blocks into larger SoC environment
Design block-level microarchitectures
Support the entire chip life from design/implement/verification/bringup/validation
Minimum Qualifications:
BS Electrical Engineering or Computer Engineering
5 years of experience as a digital design engineer using Verilog/SystemVerilog
Experience in microarchitecture development
Experience with on-chip bus protocols AXI AXI-Lite etc.
Experience with simulation tools like VCS/Verdi/Questa
Experience in multi-clock-domain designs
Experience with JTAG interface
Familiarity with Linux environment bash scripting
Experience in Python3
Preferred Qualifications:
Experience in FPGA
Experience integrating with interfaces like PCIe DDR4 MIPI
Experience with UVM
Experience in SoC integration and ASIC design
Experience with DFT

Benefit packages for this role will start on the 31st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.