Principal Signal & Power Integrity Engineer

Insight Global is looking for a Principal Signal & Power Integrity Engineer that will be working on site in Austin, TX and support a public-private partnership of preeminent semiconductor systems and defense electronics companies, national labs, and academic institutions. Their mission is to advance the state-of-the-art in critical semiconductor domains such as advanced packaging, and in the process to help restore U.S. leadership in semiconductor manufacturing. They are developing cutting-edge semiconductor manufacturing equipment and processes that will define future roadmaps of semiconductor logic, memory, heterogenous integration, chip cooling, etc. They are Backed by $1.4 billion in combined funding from DARPA, Texas state initiatives, and strategic partners, they are building foundational capabilities in advanced packaging and integrated design infrastructure to restore U.S. leadership in microelectronics manufacturing.


· Own and drive signal integrity and power integrity analysis end-to-end for advanced 2.5D/3.0D heterogeneous integration packages—from initial interconnect architecture through silicon-package co-design to final signoff.
· Perform high-speed interconnect modeling and extraction (S-parameters, RLCK, transmission-line models) across TSVs, micro-bumps, hybrid bonds, RDL, and advanced substrates (silicon, glass, organic).
· Architect and optimize power delivery networks (PDN) for multi-chiplet 3D stacks—including target impedance analysis, decoupling strategy, IR-drop simulation, and PDN resonance identification from die through package to board.
· Execute full SI simulation workflows: EM extraction, crosstalk analysis, eye diagram/BER prediction, channel compliance simulation, and jitter budgeting for high-speed interfaces (PCIe Gen6/7, CXL, UCIe, SerDes, HBM).
· Build and validate SI/PI models for the 3D Assembly Design Kit (ADK)—creating accurate, reusable electrical models that enable chiplet designers to perform system-level co-design against their integration platform.
· Develop reference flows, scripts, and automation that make SI/PI enablement repeatable and accessible to internal design teams and external customers.
· Collaborate directly with EDA vendors (Cadence, Ansys, Synopsys, Siemens, Keysight), OSATs, and foundries to develop, benchmark, and refine package-level SI/PI simulation flows and tool interoperability.
· Track and incorporate requirements from next-gen interface standards (UCIe, PCIe, CXL, UALink, OIF-CEI, HBM) into package design rules and SI/PI methodology.

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to HR@insightglobal.com.To learn more about how we collect, keep, and process your private information, please review Insight Global's Workforce Privacy Policy: https://insightglobal.com/workforce-privacy-policy/.

· 12+ years of direct, hands-on experience in signal integrity and/or power integrity engineering for advanced packaging, 2.5D/3DIC, or heterogeneous integration platforms.
· Deep expertise with SI/PI and EM extraction tools: Ansys HFSS/SIwave, Cadence Sigrity/Clarity 3D, Synopsys RaptorX, Keysight ADS/PathWave, Siemens HyperLynx, or equivalent.
· Proven ability to build and deliver package-level electrical models (S-parameters, broadband RLCK, dielectric characterization) and integrate them into design enablement and signoff flows.
· Strong understanding of high-speed signaling fundamentals: transmission-line theory, impedance matching, return-path management, crosstalk mechanisms, ISI/jitter decomposition, and equalization techniques.
· Experience with PDN design methodology: target impedance, decap optimization, plane resonance, IR-drop analysis, and SSN/SSO mitigation in multi-die environments.
· Hands-on scripting and automation skills (Python, Tcl, SKILL, etc.) to streamline simulation and extraction flows.
· BS in Electrical Engineering, Computer Engineering, Applied Physics, or related discipline.

· MS or PhD in Electrical Engineering, Applied Physics, or related discipline.
· Deep experience with multi-material package SI/PI challenges (Si interposers, glass substrates, organic build-up, Cu pillar/hybrid bond transitions) and their impact on signal loss, impedance control, and PDN performance.
· Demonstrated expertise in channel compliance and link-budget analysis for PCIe, CXL, UCIe, SerDes, or HBM, including silicon–package–board co-simulation.
· Familiarity with industry standards and working groups (IEEE, JEDEC, OIF, UCIe Consortium, 3Dblox, JEP30).
· Working knowledge of thermal and mechanical co-simulation and how thermo-mechanical effects (warpage, stress, CTE mismatch) influence SI/PI performance in 3D stacks.
· Experience creating or contributing to PDK/ADK simulation collateral for SI/PI design enablement.
· Track record of technical publications, patents, or open-source contributions in signal integrity, power integrity, or high-speed package design.

Benefit packages for this role will start on the 1st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.