Silicon DV Engineer III

Post Date

Mar 03, 2023


West Menlo Park,

ZIP/Postal Code

Aug 19, 2024 Insight Global

Job Type




Req #


Pay Rate

$89 - $108 (hourly estimate)

Job Description

Approved Meta Remote Locations: Denver CO 129.02 New York NY 150.71 Houston TX 129.02 State of CA 150.71 Redmond/Seattle WA 150.71

What are the top non-negotiable skill sets required for this role?
  • Power and performance modeling or DV C system C system Verilog or matlab
  • Strong DV background test plan development test writing UVM
  • Experience with low power verification UPF
  • Experience with both static i.e. VC LP and dynamic i.e. VCS NLP power-aware verification flows

  • Responsible for low power verification including both dynamic and static verification
  • Write and augment existing testplans.
  • Implement testbench and scoreboards / checkers.
  • Implement test sequences as per plan and debug failures
  • Achieve 100 functional code and power coverage
  • Work closely with designers micro architects f/w to resolve issues
  • Ability to communicate articulate clearly progress / issues with project leads


    Must Have:
  • 7 years of proven experience as a DV engineer
    o Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification
  • Hands on experience with SV SystemVerilog and UVM Universal Verification Methodology
  • Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
  • Experience with UPF based simulation flow
  • 2 Years of experience with C/C
  • Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM based methodologies

    Wish List/ Nice to Have:
  • Power and performance FPGA validation
  • Hifi4 TIE CNN DSP fixed point floating point SONICS python.
  • Experience with Power Aware GLS flow
  • Tcl and Python or similar scripting language
  • ASIC design experience
  • Experience in formal property verification of complex compute blocks like DSP CPU or HW accelerators
  • Experience with complex SoCs
  • Knowledge of coverage merging across simulation and formal
  • Experience with IP or integration verification of high-speed interfaces like AXI PCIe DDR Ethernet
  • MSEE/CS or equivalent experience

  • Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
  • Master's Degree preferred but not required
  • Benefit packages for this role will start on the 31st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.