Silicon DV Engineer V

Post Date

Feb 16, 2023

Location

Los Altos,
California

ZIP/Postal Code

94023
US
Jul 19, 2024 Insight Global

Job Type

Contract

Category

Engineer

Req #

VMS-MET-41804-1

Pay Rate

$111 - $135 (hourly estimate)

Job Description

Description

Approved Meta Remote Locations: Denver CO 162.35 New York NY 189.28 Houston TX 162.35 Los Angeles CA 175.25 and San Diego CA 162.35.

What are the top non-negotiable skill sets required for this role?

* Proficient in SystemVerilog C/C
* Proficient in scripting Python or Perl
* Strong DV background test writing methodology debug

Duties:

* Achieve 100 functional and code coverage through analysis test writing and exclusions
* Automate code generation for testbench using scripts
* Monitor delegate and debug nightly test regression failures
* Functional verification and performance validation of performance-related design areas
* Support integration of IP block tests into larger SubSystem or SoC environment tests
* Implement and maintain testbench and scoreboards / checkers.
* Implement test sequences as per plan and debug failures

Skills

Must Have:

* 7 years of proven experience as a DV engineer
* Hands on experience with executable test plans and coverage driven verification
* Hands on experience with SV SystemVerilog and UVM Universal Verification Methodology or equivalent
* Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
* 2 Years of experience with C/C
* 4 Years of experience with a scripting language Python or Perl

Wish List/ Nice to Have:

* Experience in GPU Display or Imaging Pipeline Silicon development.
* Experience in development System Verilog UVM testbench environment from scratch
* Experience with Software/Hardware Co-simulation DPI/VPI
* Experience with C/C modeling of the Hardware Systems
* Experience with verification of high speed interfaces like MIPI
* Experience with on-chip bus protocols AXI AXI-Lite AHB OCP
* Experience with post-silicon lab/bench test/validation
* Experience with UPF based simulation flow

Education

* Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
* Master's Degree preferred but not required

Benefit packages for this role will start on the 31st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.