Physical Design Engineer

Job Overview
We are seeking a Physical Design Engineer to support the implementation of complex ASIC/SoC designs from synthesis through tapeout. This role is responsible for physical design execution, timing closure, physical verification, DFT integration, and design optimization while collaborating with cross-functional engineering teams to deliver high-quality, manufacturable silicon.

Key Responsibilities
• Perform full-chip and block-level physical design including synthesis, DFT integration, floorplanning, power planning, placement, CTS, routing, post-route optimization, and timing closure.
• Drive timing closure across all corners and modes, addressing setup/hold, signal integrity, and IR/EM requirements.
• Develop and improve physical design and DFT methodologies, flows, and automation.
• Analyze and resolve timing, congestion, power, and implementation issues.
• Perform physical verification including DRC, LVS, and antenna checks.
• Support tapeout activities and assist with post-silicon debugging as needed.
• Evaluate and integrate third-party IP, libraries, and design tools.
• Automate repetitive design tasks using Python, Tcl, and shell scripting.
• Collaborate with RTL, verification, and other engineering teams to ensure successful design integration.

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to HR@insightglobal.com.To learn more about how we collect, keep, and process your private information, please review Insight Global's Workforce Privacy Policy: https://insightglobal.com/workforce-privacy-policy/.

Required Experience
• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of ASIC physical design experience with full-chip and/or large-block implementation.
• Proven experience with synthesis, physical implementation, timing closure, DFT integration (scan, JTAG, MBIST, LBIST), and silicon tapeouts.
• Strong knowledge of CMOS process technology, static timing analysis, timing constraints, power integrity, signal integrity, and DRC/LVS debugging.
• Hands-on experience with Synopsys Design Compiler, ICC2/Fusion Compiler, PrimeTime, and StarRC.
• Proficiency in scripting and automation using Python, Tcl, and shell.
• Strong debugging, problem-solving, and collaboration skills.

Preferred Experience
• Experience developing and improving physical design and DFT methodologies.
• Experience integrating third-party IP, libraries, and EDA tools.
• Experience supporting post-silicon validation and debugging.
• Strong communication skills and ability to manage multiple priorities in a team-oriented environment.

Benefit packages for this role will start on the 1st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.