We are seeking an experienced CMOS Layout Designer to support the physical layout of advanced high-speed digital and analog/mixed-signal blocks in cutting-edge process technologies (7nm and below, including GAA).
This role will focus on the design and assembly of parasitic-sensitive blocks for high-speed data transmission, as well as voltage regulation and logic integration at the block level.
What Youll Be Doing:
Designing and integrating parasitic-sensitive CMOS logic blocks, including high-speed driver and receiver circuits
Supporting the layout of mid-sized digital blocks, including high-speed interfaces (up to 32Gb/s or higher)
Performing block-level assembly and template-based logic integration
Collaborating with circuit designers to implement post-layout modifications and parasitic extraction feedback
Potentially supporting next-generation GAA-based voltage regulator layouts
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5+ years of hands-on mask layout experience in advanced deep submicron CMOS nodes (16nm, 7nm, 5nm, 3nm, or 2nm), with a strong understanding of modern layout challenges
Expertise using Cadence Virtuoso XL for custom digital and analog layout in a Linux-based environment
Solid experience with DRC/LVS verification flows using tools like Calibre, ICV, or equivalent
3+ years of custom analog/mixed-signal layout experience, with a strong grasp of layout-dependent effects (LDE), matching, shielding, and parasitic-aware design practices
Exposure to high-speed circuit layout (e.g., SerDes, clocking, or high-speed I/O) is highly preferred
Exposure to high-speed circuit layout (e.g., SerDes, clocking, or high-speed I/O) is highly preferred
Benefit packages for this role will start on the 31st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.