Title: ASIC/FPGA Design Verification Engineer with UVM Experience
PLEASE DO NOT SUBMIT THE SAME CANDIDATES TO THIS REQUEST AS 59531
Create UVM simulation plan from design specification. Create or modify UVC Score Board Monitor and test cases. Verify until functional coverage and code coverage meet project threshold. Document results.
Benefit packages for this role will start on the 31st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.